Amiga memory map

Contents:

• Address space
  
  
• CIA registers
  
  
• Chip registers
  
  

Address space

CIA registers

Notes:

• Timers are running at 7.15909 MHz on NTSC and 7.09379 MHz on PAL.
• Direction registers' bits sets the corresponding ports' bits' direction; 1 = output, 0 = input.
• CIAA can generate interrupt INT2 and CIAB can generate interrupt INT6.
• All unused register bits are unaffected by a write and forced to 0 on a read.

CIA Control Register

Chip registers

Note:
If both period and volume are modulated on the same channel,
the period and volume will be alternated. First AUDxDAT word
is used for V6-V0 of UDxVOL. Second AUDxDAT word is used for
P15-P0 of AUDxPER. This alternating sequence is repeated.

This reg is the audio channel x (x=0,1,2,3) DMA data buffer. It
contains 2 bytes of data (each byte is a twos complement signed
integer) that are outputted sequentially (with digital to analog
conversion)to the audio output pins. With maximum volume, each
byte can drive the audio outputs with 0.8 volts (peak to peak,type).
The audio DMA channel controller automatically transfers data
to this reg from RAM. The processor can also write directly to
this reg. When the DMA data is finished (words outputted = length)
and the data in this reg has been used, an audio channel interrupt
request is set.

This pair of registers contains the 20-bit (OCS: 18-bit) starting
address (location) of audio channel x (x = 0,1,2,3) DMA data.
This is not a pointer reg and therefore only needs to be
reloaded if a different memory location is to be outputted.

This register contains the length (number of words) of audio
channel x DMA data.

This reg contains the period (rate) of audio channel x DMA data
transfer. The minimum period is 124 clocks. This means that the
smallest number that should be placed in this reg is 124.

This reg contains the volume setting for audio channel x.
Bits 6,5,4,3,2,1,0 specify 65 linear volume levels as shown below.

HARDDIS
This bit is used to disable the hardwired vertical horizontal
window limits. It is cleared upon reset.

LPENDIS
When this bit is a low and LPE (BPLCON0, bit 3) is enabled, the
light-pen latched value(beam hit position) will be read by
VHPOSR, VPOSR and HHPOSR. When the bit is a high the light-pen
latched value is ignored and the actual beam counter position is
read by VHPOSR, VPOSR, and HHPOSR.

VARVBEN
Use the comparator generated vertical blank (from VBSTRT, VBSTOP)
to run the internal chip stuff-sending RGA signals to Denise,
starting sprites,resetting light pen. It also disables the hard
stop on the vertical display window.

LOLDIS
Disable long line/short toggle. This is useful for DUAL mode
where even multiples are wanted, or in any single display
where this toggling is not desired.

CSCBEN
The variable composite sync comes out on the HSY pin, and the
variable composite blank comes out on the VSY pin. The idea is
to allow all the information to come out of the chip for a
DUAL mode display. The normal monitor uses the normal composite
sync, and the variable composite sync &blank come out the HSY &
VSY pins. The bits VARVSTEN & VARHSYEN (below) have priority over
this control bit.

VARVSYEN
Comparator VSY -> VSY pin. The variable VSY is set vertically on
VSSTRT, reset vertically on VSSTOP, with the horizontal position
for set set & reset HSSTRT on short fields (all fields are short
if LACE = 0) and HCENTER on long fields (every other field if LACE = 1).

VARHSYEN
Comparator HSY -> HSY pin. Set on HSSTRT value, reset on HSSTOP value.

VARBEAMEN
Enables the variable beam counter comparators to operate
(allowing different beam counter total values) on the main horiz
counter. It also disables hard display stops on both horizontal
and vertical.

DUAL
Run the horizontal comparators with the alternate horizontal beam
counter, and starts the UHRES pointer chain with the reset of
this counter rather than the normal one. This allows the UHRES
pointers to come out more than once in a horizontal line,
assuming there is some memory bandwidth left (it doesn't work in
640*400*4 interlace mode) also, to keep the two displays synced,
the horizontal line lengths should be multiples of each other.
If you are amazingly clever, you might not need to do this.

PAL
Set appropriate decodes (in normal mode) for PAL. In variable
beam counter mode this bit disables the long line/short line
toggle- ends up short line.

VARCSYEN
Enables CSY from the variable decoders to come out the CSY
(VARCSY is set on HSSTRT match always, and also on HCENTER
match when in vertical sync. It is reset on HSSTOP match when VSY
and on both HBSTRT & HBSTOP matches during VSY. A reasonable
composite can be generated by setting HCENTER half a horizontal line
from HSSTRT, and HBSTOP at (HSSTOP-HSSTRT) before HCENTER, with
HBSTRT at ( HSSTOP-HSSTRT) before HSSTRT.

HSYTRUE, VSYTRUE, CSYTRUE
These change the polarity of the HSY*, VSY*, & CSY* pins
to HSY, VSY, & CSY respectively for input and output.

The patterns in the two registers are "anded" with the first and
last words of each line of data from Source A into the Blitter.
A zero in any bit overrides data from Source A. These registers
should be set to all "ones" for fill mode or for line drawing mode.

These two control registers are used together to control blitter
operations. There are 2 basic modes, are and line, which are
selected by bit 0 of BLTCON1, as show below.

This register holds the data resulting from each word of Blitter
operation until it is sent to a RAM destination. This is a dummy
address and cannot be read by the microprocessor. The transfer is
automatic during Blitter operation.

This register contains the width and height of the blitter operation
(in line mode width must = 2, height = line length). Writing
to this register will start the Blitter, and should be done last,
after all pointers and control registers have been initialized.

H = Height = Vertical lines (10 bits = 1024 lines max)
W = Width = Horiz pixels (6 bits = 64 words = 1024 pixels max)

These are the blitter size regs for blits larger than the earlier
chips could accept. The original commands are retained for
compatibility. BLTSIZV should be written first, followed by BLTSIZH,
which starts the blitter. BLTSIZV need not be rewritten for
subsequent bits if the vertical size is the same.
Max size of blit 32k pixels * 32k lines.

This register hold Source x (x=A,B,C) data for use by the Blitter.
It is normally loaded by the Blitter DMA channel, however it may
also be preloaded by the microprocessor.

This register contains the Modulo for Blitter source (x=A,B,C) or
Dest (x=D). A modulo is a number that is automatically added to the
address at the end of each line, in order that the address then
points to the start of the next line. Each source or destination has
it's own Modulo, allowing each to be different in size, while an
identical area of each is used in the Blitter operation.

This pair of registers contains the 20-bit (OCS: 18-bit) address of Blitter source
(x=A,B,C) or dest. (x=D) DMA data. This pointer must be preloaded
with the starting address of the data to be processed by the blitter.
After the Blitter is finished, it will contain the last data address
(plus increment and modulo).

This is the number (sign extended) that is added to the UHRES bitplane
pointer (BPLHPTx) every line, and then another 2 is added,
just like the other modulos.

When UHRES is enabled, this pointer comes out on the 2nd 'free' cycle
after the start of each horizontal line. It's modulo is added every
time it comes out. 'free' means priority above the copper and below
the fixed stuff (audio,sprites....).
BPLHDAT comes out as an identifier on the RGA lines when the pointer
address is valid so that external detectors can use this to do the
special cycle for the VRAMs, The SPRHDAT gets the first and third
free cycles.

BPLHWRM = Swaps the polarity of ARW* when the BPLHDAT comes out so
that external devices can detect the RGA and put things into memory
(ECS and later versions).

This controls the line when the data fetch starts for the BPLHPTx
pointers. V10-V0 on DB10-0.

These registers receive the DMA data fetched from RAM by the bit
plane address pointers described above. They may also be rewritten
by either micro. They act as an 8 word parallel to serial buffer
for up to 8 memory 'bit planes'. x=1-8 the parallel to serial
conversion ID triggered whenever bitplane #1 is written, inducing
the completion of all bit planes for that word (16/32/64 pixels).
The MSB is output first, and is therefore always on the left.

These registers contain the modulos for the odd and even bit planes.
A modulo is a number that is automatically added to the address at
the end of each line, in order that the address then points to the
start of the next line. Since they have separate modulos, the odd
and even bit planes may have sizes that are different from each
other, as well as different from the display window size.

If scan-doubling is enabled, BPL1MOD serves as the primary bitplane
modulos and BPL2MOD serves as the alternate. Lines whose LSBs of
beam counter and DIWSTRT match are designated primary, whereas lines
whose LSBs don`t match are designated alternate.

Address of bit plane DMA data. These pointers
must be reinitialized by the processor or coprocessor to point
in the beginning of bit plane date very vertical blank time.

This register controls which bitplanes are included (enabled) in
collision detection, and their required state if included. It also
controls the individual inclusion of odd numbered sprites in the
collision detection, by logically ORing them with their correspond-
ing even numbered sprite. Writing to this register resets the bits
in CLXCON2.

This reg controls when bit planes 7 and 8 are included in collision
detection, and there required state if included. Contents of this
register are reset by a write to CLXCON.

*BITS INITIALIZED BY RESET*

Note:
Disable bit planes cannot prevent collisions. Therefore if all
bitplanes are disabled, collision will be continuous, regardless
of the match values.

This address reads (and clears) the collision detection reg.
The bit assignments are :

Note:
Playfield 1 is all odd numbered enabled bit planes.
Playfield 2 is all even numbered enabled bit planes.

There are 32 of these registers (xx = 00-31) and together with the banking
bits they address the 256 locations in the color palette. There are
actually two sets of color regs, selection of which is controlled by
the LOCT reg bit. When LOCT = 0 the 4 MSB of red, green and blue
video data are selected along with the T bit for genlocks the low
order set of registers is also selected as well, so that the 4 bits-
values are automatically extended to 8 bits.This provides
compatibility with old software. If the full range of palette values
are desired, then LOCT can be set high and independent values for
the 4 LSB of red, green and blue can be written. The low order
color registers do not contain a transparency (T) bit.

The table below shows the color register bit usage.

T = TRANSPARENCY,
R = RED,
G = GREEN,
B = BLUE

T bit of COLOR00 thru COLOR31 sets ZD_pin HI, When that color is
selected in all video modes.

These registers contain a jump address.
See COPINS for a complete description.

These registers contain a jump address.
See COPINS for a complete description.

This is a-1 bit register that when set true, allows the coprocessor
to access the blitter hardware. This bit is cleared power on reset,
so that the coprocessor cannot access the blitter hardware.

This is a dummy address that is generated by the coprocessor whenever
it is loading instructions into its own instruction register.
This actually occurs every coprocessor cycle except for the second
(IR2) cycle of the MOVE instruction. The three types of instructions
are shown below.

Note:
BFD = Blitter finished disable. When this bit is true, the blitter
finished flag will have no effect on the coprocessor. When this
bit is zero the blitter finished flag must be true (in addition
to the rest of the bit comparisons) before the coprocessor can
exit from it`s wait state, or skip over an instruction. Note
that the V7 comparison cannot be masked.

The coprocessor is basically a 2 cycle machine that requests
the bus only during odd memory cycles. (4 memory cycles per in)

It has priority over the blitter and microprocessor.

There are only three types of instructions, MOVE immediate,
WAIT UNTIL, and SKIP IF. All instructions require 2 bus cycles
(and two instruction words). Since only the odd bus cycles are
requested, 4 memory cycle times are required per instruction.
(memory cycles are 280 ns).

There are two indirect jump registers COP1LC and COP2LC.
These are 20 bit pointer registers whose contents are used to modify
program counter for initialization or jumps.

They are transfered to the program counter whenever strobe address
COPJMP1 or COPJMP2 are written. In addition COP1LC is automatically
used at the beginning of each vertical blank time.

It is important that one of the jump registers be initialized and it`s
jump strobe address hit, after power up but before coprocessor DMA is
initialized. This insures a determined startup address, and state.

These address are strobe address, that when written to cause the
coprocessor to jump indirect using the address contained in the
first or second location regs described below. The coprocessor itself
can write to these address, causing it`s own jump indirect.

These registers control the horizontal timing of the beginning and
end of the bit plane DMA timing display data fetch. The vertical bit
plane DMA timing is identical to the display windows described above.
The bit plane Modulos are dependent on the bit plane horizontal size,
and on this data fetch window size.

Register bit assignment :

The tables below show the start and stop timing for different register contents

DDFSTRT (Left edge of display data fetch) :

DDFSTOP (Right edge of display data fetch) :

Note that these numbers will vary with variable beam counter mode
set: (The maxes and mins, that is).

The original Denise (8362) does not have this register, so whatever
value is left over on the bus from the last cycle will be there.
ECS Denise (8373) returns hex (fc) in the lower 8 bits.Lisa returns
hex (f8). The upper 8 bits of this Register are loaded from the
serial mouse bus, and are reserved for future hardware implentation.

The 8 low-order bits are encoded as follows :

A proposed way to detect chip's revision through hardware poking :

is_AGA:
    move.w 0xdff07c,d0    
    moveq  #31-1,d2
    and.w  #0xff,d0
check_loop:
    move.w 0xdff07C,d1
    and.w  #0xff,d1
    cmp.b  d0,d1
    bne.b  not_AGA
    dbf    d2,check_loop
    or.b   #0xf0,d0
    cmp.b  #0xf8,d0
    bne.b  not_AGA
    moveq  #1,d0
    rts
not_AGA:
    moveq  #0,d0
    rts
			

This is an added register for Hires chips, and allows larger start
& stop ranges. If it is not written, (DIWSTRT, DIWSTOP)
description holds. If this register is written, direct start & stop
positions anywhere on the screen. It doesn't affect the UHRES
pointers.

H1 and H0 values define 70ns and 35ns increments respectively, and new LISA bits.

Note:
In all 3 display window registers, horizontal bit positions have been
renamed to reflect HIRES pixel increments, e.g. what used to be
called H0 is now referred to as H2.

These registers control the display window size and position,
by locating the upper left and lower right corners.

DIWSTRT is vertically restricted to the upper 2/3 of the display (V8=0),
and horizontally restricted to the left 3/4 of the display (H8=0).

See DIWHIGH for exceptions.

This register controls all of the DMA channels, and contains
blitter DMA status bits.

This register is the Disk-Microprocessor data buffer. Data from the
disk (in read mode) is loaded into this register one byte at a time,
and bit 15 (DSKBYT) is set true.

This register is the disk-DMA data buffer.It contains 2 bytes of data
that are either sent to (write) or received from (read) the disk. The
DMA controller automatically transfers data to or from this register
and RAM, and when the DMA data is finished (length=0) it causes
a disk block interrupt.

This pair of registers contains the 20-bit (OCS: 18-bit) address of disk DMA data.
These address registers must be initialized by the processor or
coprocessor before disk DMA is enabled.

This register controls the fetch mechanism for different
types of Chip RAM accesses:

Bits 7-0 contain the stop and start positions, respectively,
for programmed horizontal blanking in 280ns increments.
Bits 10-8 provide a fine position control in 35ns increments.